View MA009AF_4772848.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ma009a 24-bit i/o extender with interrupt function this document contains information on a new product under developm ent by megawin. megawin reserves the right to change or disco ntinue this product without notice. ? megawin technology co., ltd. 2006 all rights reserved. 2006/09 version a1 megawin features ? operation voltage: 2.0v to 5.7v ? low standby current (1ua, typ.) ? 2 mbps, 3-wire serial interface ? 8 chip addresses are provided ? 24 input/output pins ? 16 input pins with pull-high disable/enable and interrupt function ? 16 output pins with cmos/nmos, large/small sink capability selection information ma009ah ma009ap ma009ad MA009AF package / dice dice 44-plcc 48-lqfp 44-pqfp parallel input 8 pins parallel output 8 pins parallel i/o 8 pins max. sink current 20ma application field system i/o port led status indicator
2 ma009a technical summary megawin general description the ma009 is high-speed si-gate cmos devices that provide a general purpose i/o peripheral. the ma009 provides microcontroller eight input pins plus eight i/o pins and eight output pins. each input pin can be configured as interrupt source and output pin can be configured as cmos/nmos output. the ma009 is controlled through a 3-wire serial interface, and can be set as one of eight chip addresses by pin option. the device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. pad description pad no. pad name i/o description 1, 8, 9 nc i no connection 2, 3, 4 a0, a1, a2 i chip address bit0, bit1, bit2 5 c/db i serial interface, command/data selector 6 sclk i serial interface, serial clock 7 sin i serial interface, serial command/data input 10 intb o input port interrupt event indicator 20 to 13 p 20 to p 27 o output port 2 29 to 22 p 10 to p 17 o input/output port 1 38 to 31 p 00 to p 07 o input port 0 12, 30, 40, 41 v cc p positive supply voltage 11, 21, 39 gnd p power ground (0 v)
megawin ma009a technical summary 3 block diagram input port p0 i/o port p1 output port p2 control logic serial to parallel converting logic c/db sclk sin intb a0 ~ a2 p0 p1 p2 vdd vss
4 ma009a technical summary megawin function description there are three 8-bit i/o ports (p0 is pure input por t, p1 is i/o port and p2 is pure output port) and one interrupt output pin (intb) in ma009. the ma009 ope rates as a slave that sends and receives data through a 3-wire interface. the interface uses a command/data select line (c/db); serial command/data line (sin) and a serial clock line (sclk) to achieve bidirectional communication between master(s) and slave(s). the master (such as microcontroller) should send serial clock and serial command to configure or to get data from ma009. the serial communication waveform are shown as below: command data c/db sclk sin command write period msb lsb command write period waveform (command should be ready in rising edge) command data c/db sclk sin command read period msb lsb command read period waveform (master can get data in falling edge)
megawin ma009a technical summary 5 control registers definition the default value of all the control register is 0 after power on. chip address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c_addr - - - - - a02 a01 a00 chip address register. only the contents of chip address register are same as chip address pin a2, a1 and a0, all command could be enabled. this function will make the master to connect more than one ma009 easily. input port 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 p07 p06 p05 p04 p03 p02 p01 p00 port p0 input status register. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0pr - - - - - - pr01 pr00 port p0 pull high control register. p0pr.0: p0.0 ~ p0.3 pull high control, 0: enable (large resistance, 350k), 1: disable p0pr.1: p0.4 ~ p0.7 pull high control, 0: enable (large resistance, 350k), 1: disable name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0psr - - - - - - ps01 ps00 port p0 strong pull high selection register. p0psr.0: p0.0 ~ p0.3 strong pull high selection, 0: disable, 1: enable (small resistance, 50k) p0psr.1: p0.4 ~ p0.7 strong pull high selection, 0: disable, 1: enable (small resistance, 50k) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0ien ie07 ie06 ie05 ie04 ie03 ie02 ie01 ie00 port p0 interrupts enable register. p0ien.0 ~ p0ien.7: p0.0 ~ p0.7 falling edge interrupts control, 0: disable, 1: enable name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0evt st07 st06 st05 st04 st03 st02 st01 st00 port p0 interrupts events status register. when a falling edge signal is occurs in any interrupt enabled (the bit 0 or bit 1 of p0ien is set to 1) pins of port p0, the corresponding bit of p0evt will be set to 1. the interrupt will be generated from the intb (1 ! 0) pin in this condition, and the mater (for example, a microcontroller) can read the interrupt status from p0evt. the master can send evtclr (13h) command to ma009 to clear the p0 evt after the interrupt event is processed. this
6 ma009a technical summary megawin function will make the mater to expand interrupt pins very easily. i/o port 1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 p17 p16 p15 p14 p13 p12 p11 p10 port p1 input or output status register. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1cr - - - - - - cr11 cr10 port p1 i/o control register. p1cr.0: p1.0 ~ p1.3 is input or output, 0: input, 1: output p1cr.1: p1.4 ~ p1.7 is input or output, 0: input, 1: output name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1por - - - - - - po11 po10 port p1 pull high/output mode control register. if p1cr.x == 0 (input mode) p1por.0: p1.0 ~ p1.3 pull high control, 0: enable (large resistance, 350k), 1: disable p1por.1: p1.4 ~ p1.7 pull high control, 0: enable (large resistance, 350k), 1: disable if p1cr.x == 1 (output mode) p1por.0: p1.0 ~ p1.3 cmos/nmo s selector, 0: cmos, 1: nmos p1por.1: p1.4 ~ p1.7 cmos/nmo s selector, 0: cmos, 1: nmos name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1psr - - - - - - ps11 ps10 port p1 strong pull high selection register. if p1cr.x == 0 (input mode) p1psr.0: p1.0 ~ p1.3 strong pull high control, 0: disable, 1: enable (small resistance, 50k) p1psr.1: p1.4 ~ p1.7 strong pull high control, 0: disable, 1: enable (small resistance, 50k) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1scr - - - - - - sc11 sc10 port p1 sink control register. if p1cr.x == 1 (output mode) p1scr.0: p1.0 ~ p1.3 output sink ability contro l, 0: weak, 1: strong (large sink current) p1scr.1: p1.4 ~ p1.7 output sink ability contro l, 0: weak, 1: strong (large sink current)
megawin ma009a technical summary 7 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1ien ie17 ie16 ie15 ie14 ie13 ie12 ie11 ie10 port p1 interrupts enable register. if p1cr.x == 0 (input mode) p1ien.0 ~ p1ien.7: p1.0 ~ p1.7 falling edge interrupts control, 0: disable, 1: enable name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1evt st17 st16 st15 st14 st13 st12 st11 st10 port p1 interrupts events status register. this function is same as port p0. when a falling edge signal is occurs in any interrupt enabled (the bit 0 or bit 1 of p1ien is set to 1) pins of port p1, the corresponding bit of p1evt will be set to 1. the interrupt will be generated from the intb (1 ! 0) pin in this condition, and the mater (for ex ample, a microcontroller) can read the interrupt status from p1evt. the master can send evtclr ( 13h) command to ma009 to clear the p1evt after the interrupt event is processed. output port 2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 p27 p26 p25 p24 p23 p22 p21 p20 port p2 output status register. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2or - - - - - - or21 or20 port p2 output mode control register p2or.0: p2.0 ~ p2.3 cmos/nmos selector, 0: cmos, 1: nmos p2or.1: p2.4 ~ p2.7 cmos/nmos selector, 0: cmos, 1: nmos name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2scr - - - - - - sc21 sc20 port p2 sink control register. p2scr.0: p2.0 ~ p2.3 output sink ability contro l, 0: weak, 1: strong (large sink current) p2scr.1: p2.4 ~ p2.7 output sink ability contro l, 0: weak, 1: strong (large sink current) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2pr - - - - - - pr21 pr20 port p2 pull high control register. p2pr.0: p2.0 ~ p2.3 pull high control, 0: enable (large resistance, 350k), 1: disable p2pr.1: p2.4 ~ p2.7 pull hi gh control, 0: enable (large resistance), 1: disable
8 ma009a technical summary megawin command definition instruction opcode operand1 data comments c_res feffh software chip reset, all register value will be reset to 0 (default value). c_evtclr 13h clear all event, p0evt and p1evt will be cleared. w_addr fdh 8-bit data write chip address, must match the pin status of a2 ~a0 to enable ma009. input port p0 w_p0pr 04h 8-bit data write p0pr (pull high control register) w_p0psr 0ah 8-bit data write p0psr (strong pull high selection register) w_p0ien 10h 8-bit data write p0ien (interrupts enable register) r_p0 3dh 8-bit data (r) read p0 r_p0pr 34h 8-bit data (r) read p0pr r_p0psr 3ah 8-bit data (r) read p0psr r_p0evt 43h 8-bit data (r) read p0evt (interrupts events status register) i/o port p1 w_p1 0eh 8-bit data write p1 w_p1cr 02h 8-bit data write p1cr (i/o control register) w_p1por 05h 8-bit data write p1por (pull high/output mode control register) w_p1psr 0bh 8-bit data write p1psr w_p1scr 08h 8-bit data write p1scr (sink control register) w_p1ien 11h 8-bit data write p1ien r_p1 3eh 8-bit data (r) read p1 r_p1cr 32h 8-bit data (r) read p1cr r_p1por 35h 8-bit data (r) read p1por r_p1psr 3bh 8-bit data (r) read p1psr r_p1scr 38h 8-bit data (r) read p1scr r_p1evt 44h 8-bit data (r) read p1evt output port p2 w_p2 0fh 8-bit data write p2 w_p2or 06h 8-bit data write p2or (output mode control register) w_p2scr 09h 8-bit data write p2scr w_p2pr 0ch 8-bit data write p2pr r_p2or 36h 8-bit data (r) read p2or r_p2scr 39h 8-bit data (r) read p2scr r_p2pr 3ch 8-bit data (r) read p2pr the command should be sent from msb to lsb, and the signal must be stable in clock rising edge.
megawin ma009a technical summary 9 command waveform example: if we want to set the p0.0~p0.3 as interrupt source, then we can write 0fh into p0ien register. all the signals are sent ma009 by master(s) in this case. command data c/db sclk sin command write period msb lsb msb lsb if we want to read the interrupt status, then we can send 43h to ma009. the last 8-bit data is sent by ma009 in this case. command data c/db sclk sin command read period lsb msb lsb msb
10 ma009a technical summary megawin application circuit ma009 vdd p2.0 p2.1 p2.2 p2.7 . . . . . . p0.0 p0.1 p0.2 p0.3 input 0 input 1 p1.0 i/o 1 i/o 0 i/o 2 p1.1 p1.2 sclk sin c/db intb a2 a1 a0 vdd gnd vcc vdd 0.1uf int sclk sdata i/o uc
megawin ma009a technical summary 11 pad assignment nc nc sin sclk c/db a2 a1 a0 nc 11 12 13 14 15 16 17 18 19 20 21 23 24 25 10 9 8 7 6 5 4 3 2 1 (0,0) 39 38 37 36 35 34 33 32 31 30 29 28 27 26 41 40 22 intb gnd vcc p27 p26 p25 p24 p23 p22 p21 p20 p17 p16 p15 p14 p13 p12 p11 p10 gnd vcc p03 p02 p01 p00 p07 p06 p05 p04 gnd vcc vcc
12 ma009a technical summary megawin absolute maximum rating parameter rating unit supply voltage to ground potential -0.3 to +6.0 v applied input / output vo ltage -0.3 to +6.0 v power dissipation 500 mw ambient operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (v cc -gnd = 5.0v, ta = 25 c; unless otherwise specified) parameter sym. conditions min. typ. max. unit op. voltage v cc - 2.0 5.0 6.0 v op. current i op no load (ext.-v) - 4.0 16.0 a standby current i stb no load (ext.-v) - 0.5 2.0 a input high voltage v ih - 0.7 v dd - v dd v input low voltage v il - 0 - 0.3v dd v p 1.0 to p 2.7 , intb normal s ink current i ol0 v ol = 0.4v - 3.0 4.5 ma intb drive current i oh0 v oh = 4.5v - 1.5 2.5 ma v ol = 0.4v - 18 27 ma p 1.0 to p 2.7 large sink current i ol1 v ol = 0.4v, v cc = 6.0v - 20 32 ma v oh = 4.5v - 2.7 3.5 ma p 1.0 to p 2.7 drive current i oh1 v oh = 5.4v, v cc = 6.0v - 3.0 5.5 ma all output ( p 1.0 to p 2.7 ) large sink current i ol2 v ol = 0.4v - 16 24 ma all output ( p 1.0 to p 2.7 ) drive current i oh2 v oh = 4.5v - 8 12 ma total out put large sink current i ol3 v ol = 0.4v - 256 384 ma total output drive current i oh3 v oh = 4.5v - 128 192 ma internal pull-high resistor (l) r ph0 weak pull high - 350k - internal pull-high resistor (s) r ph1 strong pull high, p0, p1 only - 50k -
megawin ma009a technical summary 13 ac characteristics (vcc-gnd = 5.0v, ta = 25 c; unless otherwise specified) parameter sym. conditions min. typ. max. unit maximum clock pulse frequency (sclk) f max 50 % duty cycle - 2.5 5 mhz pulse width t w sclk 100 -2 - ns command setting time t cs c/db to sclk 60 -2 - ns t ds1 c/db to sclk (write mode) 30 -2 - ns data setting time t ds2 c/db to sclk (read mode) 30 -2 - ns t su1 sin to sclk (command) 20 -2 - ns setup time t su2 sin to sclk (data) 20 -2 - ns hold time t h sclk to sin 10 -2 - ns input/output switch time t sw vdd = 2.4v - 15 ns output valid time t v vdd = 2.4v - 10 ns output hold time t ho vdd = 2.4v 20 - ns software reset recovery time t srec vdd = 2.4v 90 - ns system timing command write setup time waveforms command data c/db sclk sin command write period t w t cs t su1 t h t ds1 t su2 valid in valid in
14 ma009a technical summary megawin command read setup time waveforms command data c/db sclk sin command read period valid out valid in t v t ds2 t ho command reset recovery time waveforms command c/db sclk sin software reset period msb lsb t srec
megawin ma009a technical summary 15 package information ma009ae 48 pin pdip (600mil) configuration c/db sclk sin nc nc intb gnd vcc p27 p26 p25 p24 p23 p22 p21 p20 gnd p17 p16 p15 p14 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 p10 p11 p12 p13 nc nc nc nc p01 p02 p03 p04 p05 p06 p07 vcc a2 a1 a0 nc vcc vcc gnd p00 48-pdip (600 mil) 48 pin pdip package dimension
16 ma009a technical summary megawin ma009ap 44 pin plcc configuration vcc p27 p26 p25 7 8 9 10 p24 p23 p22 p21 p20 gnd 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 29 30 31 32 33 34 35 36 37 38 39 p10 p17 p16 p15 p14 nc nc nc p13 p12 p11 vcc p07 p06 p05 p04 p03 p02 p01 p00 gnd vcc vcc nc a0 a1 a2 c/db sclk sin nc nc intb gnd 44 pin plcc package dimension
megawin ma009a technical summary 17 ma009ad 48 pin lqfp configuration vcc p27 p26 p25 1 2 3 4 p24 p23 p22 p21 p20 gnd 5 6 7 8 9 10 11 12 p17 p16 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 25 26 27 28 29 30 31 32 33 34 35 36 p15 p14 nc nc nc nc nc nc nc p13 p12 p11 p10 vcc p07 p06 p05 p04 p03 p02 p01 p00 gnd vcc gnd vcc nc a0 a1 a2 c/db sclk sin nc nc intb 48 pin lqfp package dimension
18 ma009a technical summary megawin MA009AF 44 pin pqfp configuration vcc nc 1 2 3 4 a0 a1 a2 c/db sclk sin 5 6 7 8 9 10 11 nc nc 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 23 24 25 26 27 28 29 30 31 32 33 gnd vcc p27 p26 p25 p24 p23 p22 p21 p20 gnd p17 p16 p15 p14 nc nc nc p12 p11 p10 vcc p07 p06 p05 p04 p03 p02 p01 p00 gnd vcc intb p13 44 pin pqfp package dimension
megawin ma009a technical summary 19 vision history version date page description a1 sep. 2006 initial issue.

▲Up To Search▲

Price & Availability of MA009AF

	To Download MA009AF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .